Frameworks and engineering services to speed up and scale out ASIC development for modern, agent-assisted silicon teams.
design:
parameters:
wb_ram_data:
depth: 0x1000
memfile: "top_sram.init"
ports:
vexriscv:
clk: clk100
reset: [crg, sys_rst]
wb_uart: ...
interfaces:
interconnect: ...
Establish and enforce guardrails for human and agentic teams.
Our team can integrate Topwrap into your flow to automate the tedious wiring of custom and third‑party IP blocks, enabling faster bootstrapping and structured tracking of the entire design process.
Antmicro extends, adapts and improves Verilator, the industry's leading open source RTL simulator, to handle massive designs and complex verification workflows.
Identifying specific bottlenecks and implementing targeted improvements to reduce simulation cycles.
Verification Features
Uvm-1.2-Testbenches
Bringing the industry-standard design verification framework to the open source tooling ecosystem.
Implementing four-state logic support to achieve more accurate simulation and debugging.
RTL testing and verification
Cores-VeeR-EL2
1779 successful
2 skipped · 1 failing
Scalable, open source verification pipelines for the VeeR RISC-V core and Caliptra RoT that can be used as a template for reproducible CI workflows tailored to your custom IP.
Enabling system-level verification in a software context with Renode, we facilitate seamless HW/SW co-simulation for complex IP, demonstrated by our partnership with Google around the Coral NPU ecosystem.
FAULTERGEISTWe built Faultergeist to inject bit-flips into Verilator simulations, testing SEU vulnerability and validating fault protection for aerospace and critical applications.
As a driving force behind the project, we help standardize open source SystemVerilog tooling across testing, linting, formatting, parsing, synthesis and design verification.
We use and enhance emerging DV methodologies such as cocotb to enable a more software-driven approach to verification.
Interactive centralized coverage visualization and analysis dashboard.
View repositoryI3C coverage
i3c-core / I3CCSR.sv
input wire clk,input wire rst,input wire s_cpuif_req,input wire s_cpuif_req_is_wr,Structured verification mapping and execution tracking tool.
View repositoryi3c-core / main
86.4%A utility for generating the boilerplate code for a UVM agent, as well as the complete UVM testbench for a given DUT.
View repository$ uvmdvgen i2c -a -s
-ao hw/dv/sv --fusesoc --vendor example
i2c agent
environment
testbench
FuseSoC
Antmicro extends the open source OpenROAD toolchain to enable new, AI-first use cases.
We build flows to help teams identify bottlenecks early in the design process, enabling actionable optimizations before physical layout is finalized.
We implement advanced models directly into OpenROAD, tailoring the functionalities to meet your specific constraints.
We integrate OpenROAD into reproducible, cache-aware build systems to shorten iteration cycles and include physical design feedback early in your silicon development workflow.
Antmicro is a Premier Member of the OpenROAD Initiative. Alongside industry and academia members including Google, Siemens, and UC San Diego, we develop, maintain and foster the long-term sustainability of open source RTL2GDS tools to enable unfettered innovation.
Automated test case minimizer that isolates the exact SystemVerilog code triggering toolchain failures.
View repository Read blog noteVisualization tool for inspecting Abstract Syntax Trees for easier debugging.
View repository Read blog noteProfiling framework for evaluating bus traffic and interconnect performance.
View repository Read blog note