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May
14
2012
May 14th, 2012
SD controller driver for OpenRISC eCos

[If you are unfamiliar with the OpenRISC architecture or just want some help on setting up your OpenRISC work environment, we recommend the great tutorial from our friend Sven-Åke, working for our partner, Realtime Embedded.]

This week we are going to deal with SD card support for the OpenRISC eCos port, enabling the developer to have easily replacable, persistent storage for the platform, a welcome addition to any system. SD card support is generally scarce for the OpenRISC so this should be a good reference implementation for SD support on other OSs.

The SD Host controller used in ORPSoC is the sdcard_mass_storage_controller project from OpenCores. We have written a driver for the OpenRISC eCos that connects itself to the disk layer and commited it to the main OpenRISC eCos repository.

Thus it is very easy to configure eCos to support a filesystem on the SD card out of the box. In the Open Source eCos version we can choose between two popular filesystems: jffs2 and FAT.

For example, to prepare an eCos build with the FAT filesystem support, the following lines are necessary:

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ecosconfig new orpsoc default
ecosconfig add CYGPKG_IO_DISK
ecosconfig add CYGPKG_IO_FILEIO
ecosconfig add CYGPKG_FS_FAT
ecosconfig add CYGPKG_BLOCK_LIB
ecosconfig add CYGPKG_LINUX_COMPAT

Before compilation it might be a good idea to configure some options, especially the name of the disk device, which defaults to /dev/mmcdisk0.

Once we’re ready, just like in last week’s post, we issue:

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ecosconfig tree make

getting a compiled eCos with SD support. Also here the API is POSIX-compliant, which makes writing programs manipulating filesystems on SD cards easy and straightforward. A good example can be found in: packages/fs/fat/current/tests/fatfs1.c.

Note that in addition to the opencores repository, we’re now mirroring it on our github account for greater availability.

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Posted in FPGA, OpenRISC, Operating Systems, Softcore, eCos | No Comments »

May
13
2012
May 13th, 2012
Xilinx X-Fest 2012 in Oslo – time for Zynq

Oslo is always a good and familiar place to visit, especially if it means bumping into some old friends from the FPGA world and making a few new ones on a Xilinx X-Fest. The one we attended was held in Sandvika in suburban Oslo on May 8, but you can still participate in several other places around Europe and the world if you wish – check the event website!

This year, X-Fest is dominated by the new Cortex-A9+FPGA hybrid – Zynq, with one track and most exhibitor’s booths dedicated exclusively to this technology. And rightly so!

The “Processing System + Programmable Logic” combination, a dual-core general-purpose CPU with the ability to delegate tasks which are computationally heavy and prone to parallelising onto a dedicated block synthesised within the FPGA is just brilliant. Sure, not all applications will benefit from this, but if you know what you are doing and are able to identify bottlenecks in your product, you can get your software to run some 10x faster.

It’ll be good to verify this claim in practice – after all, ground-breaking technologies are more often announced than functional – but this time it looks that Xilinx’s has really done a good job. There are limitations such as power-up time or the speed of the CPU (the dual-core Cortex-A9 is clocked only around 600 MHz for now, 800 MHz in future chips) but none of them seem to be deal-breakers.

We will see if the tools available allow the ecosystem to suck up ‘traditional’ software developers in addition to the FPGA guys, but it seems that Xilinx is aware of the fact that SW engineers require a different approach and are working with ARM provide tools necessary to facilitate the transfer from plain-ol’ CPU systems to a CPU+FPGA hybrid.

We have already been running the Zynq QEMU port out of curiosity, but this of course gives little feel of what the real stuff behaves like. However, with a bit of luck we will get our hands on physical modules as early as in June.

Follow our blog where we will describe our work with the Zynq technology and our thoughts on how useful it really is in practice. If you have ideas on how your applications can benefit from using Zynq or want to ask a question about it, be sure to leave a comment!

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Posted in ARM, Events, FPGA | No Comments »

May
09
2012
May 9th, 2012
OpenRISC Ethernet driver for eCos RTOS

We have been maintaining the eCos real-time OS for openRISC for some time now, but what has been an obstacle to use it in a wider array of applications was the lack of suitable driver support enabling the construction of a platform featuring a richer set of interfaces.

In a series of posts, we have decided to amend this situation by writing, contributing and showing how to use drivers for some essential peripherals for ORPSoC.

The first peripheral we are going to work with is Ethernet.

We have written drivers to support OpenCores ethmac Ethernet controller (http://opencores.org/project,ethmac). It is already commited to main OpenRISC eCos repository which we’re maintaining.

The driver for the Ethernet controller will be automatically added to the eCos build if we select any network stack. We can pick from the following:

– TCP/IP stack from OpenBSD
– TCP/IP stack from FreeBSD (including KAME IPv6)
– Lightweight TCP/IP stack: lwIP (note: originally created by Adam Dunkels at the Center for Networked Systems at SICS, with whom we cooperate)

For example, in order to build eCos with the FreeBSD stack, the following steps have to be taken:

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ecosconfig new orpsoc default
ecosconfig add CYGPKG_NET
ecosconfig add CYGPKG_NET_FREEBSD_STACK
ecosconfig add CYGPKG_IO_FILEIO
ecosconfig add CYGPKG_IO_ETH_DRIVERS

Before we proceed to compilation, we need to do some additional configuration of the driver and the network stack. The most important configuration options are of course the MAC address of the Ethernet controller itself as well as the IP address (either static or dynamically allocated via DHCP) of the device. The configuration can be done in two ways: either using the GUI program, configtool, or via editing ecos.ecc.

When we are done, we should issue:

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ecosconfig tree
make

which results in a compiled eCos with Ethernet and TCP/IP support. The nice thing is that the network services API in eCos is POSIX-compliant, so the networking programs look and work just like Linux ones. It is best to look at some examples, residing in the packages/net/common/current/tests/ directory – especially ping_test.c and server_test.c are worth noting.

Note: the code described in this post is available here.

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Posted in FPGA, News, OpenRISC, Operating Systems, Softcore, eCos | No Comments »

May
03
2012
May 3rd, 2012
Ant Micro becomes Freescale Alliance Member

In the last post we wrote that April was a very interesting month with lots of things happening.

And so it was – thanks to the help of the wonderful people at Freescale Semiconductors Nordic AB whom we had the pleasure of meeting again at SEE (a short relation of the event will hopefully follow) we could complete our Freescale DAP application process, thus confirming our expertise in working with Freescale ARM and PowerPC products.

Freescale Alliance Member logo

So, without further ado, we are proud to announce that we are now officially a Freescale Alliance Member, one of the two such in our country. We provide third-party support (software and hardware design services) to companies using Freescale products locally as well as in Germany and the Nordic countries.

See also our description at Freescale’s website.

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Posted in News | No Comments »

Apr
29
2012
April 29th, 2012
Swedish Internet of Things Centre application filed

April came and went blazing fast due to how much was going on, both internationally and here at Ant Micro. One of the highlights of the month was the putting together of the Swedish Internet of Things Centre application, which is now filed and waiting for a green light – we’re keeping our fingers crossed!

The consumer-oriented IoT centre, with joint participation of universities, research institutes, municipalities as well as large and small companies is undoubtedly a fantastic idea but is facing a strong competition from other great projects. Undoubtedly whether or not we are one of the lucky 20, it is certain that the expression of the will to cooperate between so many partners in this interesting field is a good thing in itself, and cooperation within the consortium is already taking place.

When it comes to the project itself, Ant Micro has declared a 500 000 SEK contribution in kind, delivering it’s know-how in virtual platforms for new Internet of Things devices. We are hoping that with our input we can share in the realization of the vision of service-oriented IoT systems. And after the very positive reaction to our presence at the IoT day we were encouraged to participate all the more.

You will be able to track the results of the project at SICS’ and Vinnova’s site.

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Posted in News | No Comments »

Mar
23
2012
March 23rd, 2012
eCos-3.0 port to OpenRISC tracking mainline

Recently we have ported eCos-3.0 for the openRISC, and in other posts described how to reset the ordb2 board and how to build programs for it in the eCos.

We are hoping that this will be a solid piece of help for those who want to work with OpenRISC with a real-time operating system, and for those who want to use the new devboard from opencores.

Now the port has been updated to track the eCos mainline, thoroughly tested – passing all tests on the ordb2 board – and is hosted on OpenCores SVN.

Detailed instructions on using the port are published on the official wiki page.

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Posted in OpenRISC, eCos | No Comments »

Mar
13
2012
March 13th, 2012
Running eCos on the OpenRISC ordb2 board

UPDATE: the eCos for OpenRISC is now tracking mainline eCos and more configurations are tested, so the whole procedure was a bit simplified!

Downloading the new version of eCos will be described in a new note and linked to here.

Ant Micro is maintaining and developing the eCos port for OpenRISC – you can find the wiki page of the port at the opencores server.

So far, the port was being tested in the or1ksim simulator which is considered a golden model of the OpenRISC1000 architecture. However, it’s always best to see how a port performs on real hardware.

Recently, ORSoC shared the new ordb2 development board with us. The board is based on Altera Cyclone IV E FPGA chip and is equipped with all popular interfaces.

To verify that everything works fine, we tested the eCos port on the board by running a set of eCos tests and simple multi-threaded programs.

Below are the instructions how to run eCos programs on ordb2 board. UPDATE: Not all configuration options are yet supported, but the default configuration is well tested and stable, so the .ecc file provided previously is no longer needed.

In order to build eCos for ordb2, follow these instructions:

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mkdir ecos_openrisc
cd ecos_openrisc
ecosconfig new orpsoc
ecosconfig tree
make
make tests

After issuing these commands tt is possible to run eCos tests on the board. In order to upload the binaries using GDB, the or_debug_proxy program is needed.

Please note that FT4232 support was added to or_debug_proxy on 16th september 2011 – older builds will not work.

To establish a connection with board, issue the following command:

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or_debug_proxy -r 50001

This will open a tcp port for the GDB RSP connection.

It is now possible to open a UART connection. Please note, that it is better to open the UART connection after starting or_debug_proxy. It is because or_debug_proxy causes the system to reorder USB devices when connected to the FTDI chip.

The configuration file assumes that the UART is running at a 115200 baud rate.

To open a UART device using picocom, issue the following command:

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picocom -b 115200 /dev/ttyUSB1

The number next to ttyUSB may be different across systems.

Everything is ready to upload a test binary. We will use GDB and connect to or_debug_proxy.

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or32-elf-gdb [test binary]
target remote :50001
load
spr npc 0x100
c

Now that we know how to connect to the board, let’s make a simple hello world application. A minimal eCos hello world program looks pretty standard:

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#include <stdio.h>
int main(void) {
  printf("hello world\n");
  return 0;
}

To build the program, use the following flags with or32-elf-gcc:

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or32-elf-gcc \
   -g \
   -Iecos_openrisc/install/include \
   -Lecos_openrisc/install/lib \
   -nostdlib \
   -Tecos_openrisc/install/lib/target.ld \\
   main.c

It is now possible to upload the resulting binary file the same way described above. Have fun programming for eCos on the openRISC devboard!

Tags: , ,
Posted in OpenRISC, eCos | No Comments »

Mar
09
2012
March 9th, 2012
System reset in OpenRISC ordb2 board

The new OpenRISC ordb2 from ORSoC is a very nice devboard to have, especially with its support of multiple services like FPGA JTAG, OpenRISC JTAG and UART with a single USB cable. Our sincere thanks go to ORSoC for making a copy available to us.

For all its ease of use, the one thing that turned out to be a bit problematic was resetting the board, as no reset button is provided. The reset pin is routed to the expansion connector, but that’s not particularly helpful.

The reset line is also connected to the FT4232 controller. It is therefore possible to perform a system reset using the USB connection. Unfortunately, or_debug_proxy does not provide such functionality.

We have come up with a simple way of resetting the board using the USB connection based on the UrJTAG project, and we’d like to share it for the convenience of everyone who is getting a bit frustrated with unplugging the board time and again.

UrJTAG is a universal tool for comunicating over JTAG. It is used to program the Altera FPGA chip, as instructed in the Running_SW_on_FPGA_board.txt document (delivered inside the VirtualBox image). We shall use this tool, with a slight modification, to reset the board.

The scripts included in the VirtualBox image use a generic ft2232 cable driver. This driver does not support TRST ans SRST signals. We have written a small patch that adds a new cable called ordb2. This new cable is based on a generic ft2232 cable, except that a SRST line is added.

Below are the instructions how to enable the reset functionality in UrJTAG:

First download the UrJTAG project and two attachments of this post – the patch and the UrJTAG script.

Extract the project and apply our patch.

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tar -xvjpf urjtag-0.10.tar.bz2
cd urjtag-0.10
patch -p1 < ../urjtag-0.10-ordb2-antmicro.patch

Now build the project and copy the configuration script:

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./configure
make
cp ../ordb2_reset.cmd ./

It is now possible to reset the board, by issuing the following command (in the current directory):

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./src/jtag ordb2_reset.cmd

How convenient!

Attached .patch file: urjtag-0.10-ordb2-antmicro.patch

Attached .cmd file: ordb2_reset.cmd

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Posted in OpenRISC | No Comments »

Jan
24
2012
January 24th, 2012
Swedish Internet of Things Day in Stockholm

As a result of our continued interest in smart devices and the Internet of Things as well as cooperation with Swedish universities and research institutions, we were honoured with the invitation to participate in the creation of a new initiative – the Swedish Inernet of Things Centre, whose beautiful logo you can see above. The main actor behind the initiative, SICS, wants to give the project a kick-start in the form of a very promising event, the Internet of Things Day in Stockholm, on February 9.

Several hundred people are expected to attend, among them representatives of other companies and institutions that co-create the SIoTC – with Ericsson, Microsoft, KTH, Mobile Life, Stockholm University, Wisenet, Swedish ICT, Company P, Vendolocus and ourselves among them – which makes the SIoT Day a very interesting place to find connections and partners in IoT-related projects, as well as learn what’s ‘in’ in this pretty hot topic.

We’ll also be co-hosting one of the poster/demos during the 15.15 session, but more info on that later!

The full agenda
9.30 Welcome, Christer Norström, CEO of SICS
9.35 Why a consumer-oriented Internet of Things centre in Sweden?, Kristina Höök, head of the centre
10.00 Keynote by Bu Fanjin, deputy Chief Engineer of CEST, Ministry of Industry and Information Technology of China: China Internet of Things Plan 2011-2015
10.45 Keynote by Mike Kuniavsky, Orangecone, US: The Internet of people: integrating Internet of Things technologies is not a technical problem
11.30 Living with Internet of Things, Oskar Juhlin, Mobile Life
12.00 Lunch
13.00 Device software challenges, Adam Dunkels, SICS
13.30 Big data challenges, Ali Ghodsi, KTH
14.00 Finding values in big data, Jan Höller, Ericsson Research
14.30 Allowing everyone to create embedded systems, Steve Hodges, .NET Gadgeteer
15.00 A training app for the Swedish Olympic cross country ski team, Christer Norström
15.15 Coffee and demos

For more info, visit http://www.sics.se/Internet_of_Things_Day

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Posted in Events | No Comments »

Oct
31
2011
October 31st, 2011
eCos-3.0 port for OpenRISC

During our work with the OpenRISC platform we were missing our favourite real-time operating system – eCos. Although some porting work had been performed earlier, the eCos port was no longer supported. With the development of the OpenRISC project, as a result of toolchain and other changes, it had stopped working.

Also, it was based on the now obsolete 2.0 version of eCos.

We decided that a freshly updated eCos port could be useful both in our work and for the OpenRISC community, and here it is!

On http://opencores.org/or1k/ECos you will find the associated wiki page and from there you can download the code, of which Piotr Skrzypek is the maintainer.

Tags: ,
Posted in OpenRISC, eCos | 2 Comments »

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